The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a plurality of memory cell arrays.
Historically speaking, in a dynamic RAM device, a multiplex system is utilized for designating the memory locations. In this multiplex system, the memory address signal is divided beforehand into two address signals, i.e., row and column address signals. These row and column address signals are supplied to address pins of the dynamic RAM at different times. Where the dynamic RAM has the same memory capacity as that of, a static RAM, this dynamic RAM only requires half the number of address pins as the static RAM. When account is taken of the fact that the size of an IC package depends greatly upon the number of package pins such as, for example, address pins, the dynamic RAM is suitable for miniaturization of the package as compared with the static RAM. As far as the present is concerned, where the dynamic RAM has a memory capacity of, for example, 16K to 256Kbits, its memory chip (i.e., the semiconductor chip formed with a memory circuit) can be formed in a Dual In Line Package (DIP) having sixteen package pins and a width of 300 mil (7.62 mm).
The known types of the packages include, ceramic packages, plastic packages, sur-DIP packages, etc. Among these packages, the plastic package is most suitable for mass production and its manufacturing cost is low. The plastic package has a lead frame for connecting its memory chip to external circuits, and is constructed such that the memory chip is mounted on the lead frame, and is molded from plastic. In the case of the DIP package, in particular, the width of the memory chip is limited by the size of the lead frame used. When the memory chip is narrow, the layout of memory cells and peripheral circuits is not easy. Where the memory capacity of the dynamic RAM is increased up to, for example, 1 Mbit to 4 Mbit, it is necessary to make the size of the memory chip large, or to make the size of a memory cell small. When a DIP having a width of 300 mil is used, it is impossible to increase the size of the memory chip for the above-mentioned reason. For example, one memory cell is composed of one transistor and one capacitor. When these memory cells are formed at small intervals, the capacitance of these capacitors is decreased. This also results in a decrease in the reliability of the memory cell. When the capacitance of the capacitor is small, it is impossible to obtain a signal at a sufficiently high voltage level. In addition, software errors increase, which result from the electric charge within the capacitor being cancelled by the .alpha. rays which have temporarily been generated within the semiconductor element.
Next, the disposition of memory cell arrays and bonding arrays within the area of a memory chip will be explained with reference to FIGS. 1 and 2. In FIG. 1, a memory chip 10 is received in a ceramic DIP and bonding pads 12A and 12B are disposed on those portions of the memory chip 10 which are located along short sides 14A and 14B thereof, respectively. Further, memory cell arrays 16A to 16D are formed on the memory chip 10 in such a manner that they are extended to the neighborhoods of long sides 14C and 14D thereof. The reason why this disposition is adopted is as follows. Namely, where the ceramic DIP is used and when, in this case, the bonding posts are disposed along the long sides of its chip, since the thickness of the ceramic layer along the long sides can not be made thinner than 1 mm or so, the effective width of the chip along the short sides thereof is disadvantageously narrowed. For this reason, in the case of a ceramic DIP, the bonding posts are usually concentratedly disposed along the short sides of its chip. On the other hand, in the case of a plastic DIP such as that shown in FIG. 2, the bonding posts are disposed along the long sides, as well, of its chip because a lead frame must be disposed on one plane. In FIG. 2, a memory chip 20 is received in the plastic DIP. Bonding pads are formed on the peripheral part of this memory chip 20. Memory cell arrays 24A to 24D are surrounded on the semiconductor chip 20 by these bonding pads. If, in case the plastic DIP is used, the bonding pads are all formed on those portions of the memory chip which are located along the short sides thereof, bonding wires having a large length must be used as the bonding wires for connecting those bonding pads and a lead frame. In this case, however, defective connections are liable to be produced in the bonding step, or breakage of the bonding wires is likely to occur.
The bonding pads which are shown in FIG. 3 have a width of 100 to 130 .mu.m. Taking the bonding errors into consideration, these bonding pads are provided such that they are spaced 30 to 50 .mu.m from the sides of a memory chip, and from memory cell arrays as well. For this reason, the memory cell arrays are formed such that they are spaced from the long sides of the memory chip 20 by a distance D1 of about 200 .mu.m. In FIG. 3, the width of the memory cell region (about 400 .mu.m) is limited to a value which is smaller than the length of the short side of the chip. Therefore, where the memory capacity is as large as 1 Mbit, 4 Mbit, etc., it is difficult for the plastic DIP, having a width of 300 mil to receive the memory chip without the element characteristics deteriorating.